CPLDs: What Are Today's Challenges?
A number of challenges are faced by the users and manufacturers of ultra-low-density devices (ULDs).
View ArticleA Chess-Playing FPGA: Tree-Traversing State Machine
Following our evaluations, the resources required by a chess-playing FPGA implementation would seem reasonable, even for a small or midsized device.
View ArticleCPLDs: What Does the Future Hold?
What might we see in new Ultra Low Density (ULD) CPLD families three-to-five years down the road? Are there new technologies or programmable structures that will find their way into ULD devices?
View ArticleA Chess-Playing FPGA: Let the Coding Begin!
Warren has finally started to write some HDL code to implement his chess-playing FPGA, but he's not a professional coder, so he needs our help and advice.
View ArticleImplementing SerDes for FPGAs: More Challenges
When traversing serial links with optics or backplanes, high-speed signals are degraded by impairments in the link, such as insertion loss, reflections, crosstalk, and optical dispersion.
View ArticleA Chess-Playing FPGA: The First Testbench!
Is the low-level module testbench described here sufficient, or is there a better approach? Should a self-test testbench be used? How important are concepts like portability, ease of understanding, and...
View ArticleImplementing SerDes for FPGAs: More Challenges, Part 2
Now we are ready to consider the equalization, adaptation, and 2D eye scan blocks used in the receiver portion of a high-end FPGA transceiver.
View ArticleA Chess-Playing FPGA: Generate, Propagate & Attack!
In this blog we consider the attack logic for a single square; this can then be replicated to create the entire 64-square chess board.
View ArticleChess-Playing FPGAs at Design West 2014?
My goal is to hold a chess-playing extravaganza at Design West 2014, in which FPGA-based and/or MCU-based "Robots" compete for a grand prize.
View ArticleChess-Playing FPGA/MCU Tournament: Rules & Regulations
In order to get a chess-playing FPGA/MCU tournament up and running, we need to establish some rules and regulations.
View ArticleThe Future of FPGAs: A Retrospective
It's time to look back at our thoughts on future trends to try and make some specific predictions.
View ArticleWant to Help Define the Next Level of Programmable Devices?
Previous discussions have left Warren thinking about a possible evolutionary path for the next level of programmable devices.
View ArticleA Chess-Playing FPGA: Selecting the Best Opening Moves
In which we use the wealth of known chess openings to improve the first few moves of our chess-playing FPGA, and we also learn how these techniques can be used in many different types of embedded designs.
View ArticleA Chess-Playing FPGA: Improving the Evaluation Function
Our original concept of the chess-playing FPGA's Evaluation Function was based only on the pieces on the board. However, this is not a good technique during the opening where there is little chance for...
View ArticleA Checkers-Playing FPGA: Introduction
I have seen a few comments on playing checkers instead of chess with an FPGA. Can we use the same approach to play checkers? You bet!
View ArticleAn FPGA With Boatloads of On-Chip Memory: What Could You Use It For?
What advantages could we obtain if we had access to a very large LPDDR3 SDRAM component on an FPGA?
View ArticleAn FPGA With Boatloads of On-Chip Memory: Architectural Details
In Warren's previous post, we considered the concept of an FPGA with lots of on-chip memory. Now, let's look at a proposed architecture in more detail to see if it might be implementable.
View ArticleA Checkers-Playing FPGA: Prototyping Passionately
Although it might seem unlikely, a checkers-playing FPGA may make a good prototype for our chess-playing FPGA.
View ArticleA Checkers-Playing FPGA: Attack (Redux)
When prototyping a design, you hope to use the bulk of your code in the final design. Using checkers to prototype our chess-playing FPGA will allow us to do just that.
View ArticleA Checkers-Playing FPGA: Attack Generation Code!
The first of our prototype code that uses checkers to test out our chess algorithm demonstrates the similarities in the architectures!
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