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A Chess-Playing FPGA: Game Theory Quick Start Guide

Before we dive deeper into the "guts" of our chess-playing FPGA design, we will first need to brush up on some aspects of game theory.

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A Chess-Playing FPGA: Move Generation

When you first think about generating chess moves in hardware, it's natural to think about using a sequential process, but a parallel approach can offer significantly higher performance.

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A Chess-Playing FPGA: Best Move Logic

We begin to consider the logic used to implement a portion of the move generator function. In particular, we focus on the logic used to determine the value of the best move for a particular square.

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A Chess-Playing FPGA: Best Move Logic, Part 2

We are ready to consider how various attack signals can be generated from the value of the piece in a square.

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A Chess-Playing FPGA: Exception Conditions

We need to look closely at some exceptions to the general move case, including initial pawn moves and en passant captures.

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A Chess-Playing FPGA: Exception Conditions, Part 2

In this column, we consider how to handle the last two "exceptions" to the regular chess moves -- pawn promotion and castling.

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A Chess-Playing FPGA: Peering Into the Future

In many cases, a "greedy" strategy (just taking the opponent's biggest piece with our smallest piece) isn't sufficient to play a good game. It may be that not taking a piece will be the better move.

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A Chess-Playing FPGA: The Evaluation Function

We are now ready to consider implementing an evaluation function that determines the "state" of the board (i.e., who is winning). There are, of course, several approaches we might use...

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A Chess-Playing FPGA: The Evaluation Function, Part 2

In this blog we figure out how many bits we need to store our board value, along with any other requirements we need to place on our Evaluation Function.

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SerDes for FPGAs: Where Have We Been?

In many applications, SerDes is the most critical element, and the FPGA just supplies the "glue logic." In other cases, SerDes just supplies a convenient way to interconnect the FPGA to the outside world.

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A Chess-Playing FPGA: Linking the Move Generator & Evaluation Functions

Now that we have a Move Generator and an Evaluation Function, how do we use them to traverse the tree of all possible moves to determine the best move from a given position?

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SerDes for FPGAs: What Are Today's Challenges?

One of the most obvious challenges is the increasing number of serial communications standards that an FPGA must be able to address -- legacy, established, and emerging.

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A Chess-Playing FPGA: Generating More Moves

Our new move-generation approach is borrowed from a typical MCU interrupt function, which will allow us to generate all possible moves from a given position.

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SerDes for FPGAs: What Are Today's Challenges? Part 2

As FPGA manufacturers have become increasingly involved in SerDes standards creation, it has been possible to cover more standards with a smaller number of special blocks. Two good examples are Signal...

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A Chess-Playing FPGA: Making Moves

We've reached the stage where we need some way to move pieces around within our cellular array. How do we do this?

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SerDes for FPGAs: What Does the Future Hold?

As performance continues to scale, it seems clear that a "one size fits all" approach simply isn't possible.

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Designs Gone Wrong

Using a "methane battery" to power the electronics in a cow health monitoring system seemed like a good idea, until things started to go horribly wrong...

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A Chess-Playing FPGA: Making Moves, Part 2

In addition to working out what the best move is, we also need to keep track of the original address of the aggressor (attacking) cell so that we can replace it with a blank value.

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CPLDs: Where Have We Been?

For many applications, CPLDs are the unsung heroes of the programmable world.

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A Chess-Playing FPGA: Traversing the Tree

We are ready to consider how to use our Move Generator to traverse the tree of possible moves efficiently and find the sequence that produces the best board position.

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